PCI-T32MF: 32-bit, 33 MHz Multifunction Target Interface Core
Block Diagram

Overview
The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (PCI clock). The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2008 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog; VHDL |
Testbench language | Verilog; VHDL |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | AXI; Avalon-MM; Other: Generic uP |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, Questa, NC-SIM |
Hardware validated | Y. Altera Board Name Cyclone IV |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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