From CAST Inc.

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Documentation

PCI-T32MF: 32-bit, 33 MHz Multifunction Target Interface Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Interface Protocols: PCI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV

Segments:

Supported Device Family:

Solution Type:

Overview

The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (PCI clock). The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.

Features

Support all interrupt pins, all Base Address Registers, and backend initiated target retry, disconnect and abort
Zero wait states burst mode, type 0 configuration space and parity generation and parity error detection
PCI specification 2.3 compliant Target, 33 MHz operation 32-bit datapath

Device Utilization and Performance

The core synthesizes to about 550 LEs

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released	2008
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog; VHDL
Testbench language	Verilog; VHDL
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	AXI; Avalon-MM; Other: Generic uP
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim, Questa, NC-SIM
Hardware validated	Y. Altera Board Name Cyclone IV
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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