PCi-M32: 32-bit, 33 MHz PCI Master/Target Interface Core
Block Diagram
Overview
The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development. The PCI-M32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3. The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are: - Configuration Read, Configuration Write - Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL) - I/O Read, I/O Write
Features
- PCI specification 2.3 compliant Master/Target, 33 MHz operation (66 MHz optional), 32-bit datapath
- Zero wait states burst mode
- Support of backend initiated target retry, disconnect and abort
- Parity generation and parity error detection
- DMA Controller Core supporting independent write and read operations available
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2008 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim, Questa, NC-SIM |
| Hardware validated | Y. Altera Board Name Cyclone IV, Cylcone V |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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