PCi-M32: 32-bit, 33 MHz PCI Master/Target Interface Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: Interface Protocols: PCI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV


The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development. The PCI-M32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3. The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are: - Configuration Read, Configuration Write - Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL) - I/O Read, I/O Write


  • PCI specification 2.3 compliant Master/Target, 33 MHz operation (66 MHz optional), 32-bit datapath
  • Zero wait states burst mode
  • Support of backend initiated target retry, disconnect and abort
  • Parity generation and parity error detection
  • DMA Controller Core supporting independent write and read operations available

Device Utilization and Performance

The core synthesizes to about 650 LEs

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Year IP was first released2008
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportN/A
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated Y. Altera Board Name Cyclone IV, Cylcone V
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.