From CAST Inc.

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Documentation

LIN Bus Master/Slave Controller Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Industrial, Military

Evaluation Method: OpenCore, OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The LIN core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. The LIN controller can be implemented as a master or as a slave and operate on LIN 1.3, 2.0, 2.1 or 2.2 LIN network. It uses a single master/multiple slave concept for message transfer between nodes of the LIN network. The message transfer can be controlled via a micro controller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN core is a microcode-free design developed for reuse. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production proven multiple times.

Features

Supports of LIN specification 2.0, 2.1, and 2.2A, and is backwards compatible with LIN specification 1.3
Configurable for support of master or slave functionality
Programmable data rate between 1 Kbit/s and 20 Kbit/s (for master)
Automatic bit rate detection (for slave)
Production proven multiple times

Device Utilization and Performance

The core synthesizes to about 700 LEs.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog; VHDL
Testbench language	Verilog; VHDL
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	Other: 8-bit generic uP
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim, Questa, NC-SIM
Hardware validated	Y. Altera Board Name DE0 Nano
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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