Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Intel® Stratix® 10, Stratix® V
The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.
The JPEG-LS-E core delivers the full compression efficiency of the standard in a compact and easy-to-use hardware block. The core interfaces to the system via standardized AMBA® interfaces: it accepts images and outputs compressed data via AXI4-Stream interfaces, and provides access to its control and status registers via a 32-bit APB interface. After its registers are programmed, the core can encode an arbitrary number of images without requiring any further assistance or action from the system. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.
Highly Efficient Lossless & Near-Lossless Compression compliant to JPEG-LS, ISO/IEC 14495-1 standard
Easy to Use and Integrate: Run-time programmable input and encoding parameters – Automatic program-once encode-many operation – AXI4-Stream interfaces
Suitable for ultra-high frame-rates and/or resolutions thanks its scalable-throughput architecture. 1 to 24 samples/cycle
Complete and High-Quality deliverables, including shelf-checking test-bench, Bit-Accurate software model, and comprehensive documentation
Device Utilization and Performance
The JPEG-LS-E can be mapped to any Altera device, provided sufficient silicon resources are available. The FPGA resources required for its implementation and its throughput depend on its configuration. A basic 1 sample/cycle configuration of the core requires 5,600 ALMs and provides over 200 Msamples/sec on an Arria10 device. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
Contact CAST at firstname.lastname@example.org to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Software Bit Accurate Model
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
Y. Altera Board Name Aria10-GX Devkit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.