JPEG-LS-D: Lossless & Near-Lossless JPEG-LS Decoder

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V


The JPEG-LS-D core implements a lossless and near-lossless image decompression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard. The decoder core can decompress any JPEG-LS stream or JPEG-LS payload of image container formats, such as DICOM. It accepts compressed streams of images with up to 16-bit per color samples and up to four color components, in all widely used color subsampling formats. Supporting oversize image dimension parameters, the core can decode image with resolutions exceeding 64k x 64k pixels. The easy-to-use JPEG-LS-D core operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The core accepts compressed data and outputs pixel data, and passes metadata to the system via AXI4-Stream interfaces, and it provides access to its control and status registers via a 32-bit APB interface. A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.


  • Highly Efficient Lossless & Near-Lossless Decompression Engine compliant to JPEG-LS, ISO/IEC 14495-1 standard
  • Easy to Use and Integrate: Requires no programming or control from host – Reports image format and marker syntax errors to the system – AXI4-Stream i
  • Suitable for ultra-high frame-rates and/or resolutions thanks its scalable-throughput architecture.
  • Synthesis-time configurable number of samples per clock cycle (1 to 24 – assumes use of restart markers in JPEG-LS stream).
  • Complete and High-Quality deliverables, including shelf-checking test-bench, Bit-Accurate software model, and comprehensive documentation

Device Utilization and Performance

The JPEG-LS-E can be mapped to any Intel FPGA device, provided sufficient silicon resources are available. The FPGA resources required for its implementation and its throughput depend on its configuration. A basic 1 sample/cycle configuration of the core requires 3,800 LUTs and provides over 50 Msamples/sec on an Arria10 device. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements

Getting Started

Contact CAST at to arrange for a core evaluation

IP Quality Metrics

Year IP was first released2017
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Software Bit Accurate Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name Aria10-GX Devkit
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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