Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
This IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with very low processing latency.The JPEG-E-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it synthesizes to about 3,500 ALMs.The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access.
Input format: 8bit per color, up to 4 color-components in all widely used subsampling format, and resolution up to 64kx64k
Fully programmable markers and ending options: up to 4 Huffman Tales, up to 4 Quantization tables, APP, COM, and Restart marker segments.
Rate control optionally supported. Bit rate is regulated on either each frame basis or over a number of frames (suitable for video streaming).
Performance and Size: One color-sample per cycle, and about 3.5k ALMs. Fits even in small Intel® Max®10 devices
Device Utilization and Performance
The JPEG-E-S core can be mapped to any Intel® FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. The size of the core depends on its configuration. Under its default configuration it occupies approximately 3,500 ALMs, 4 DSPs and 50Kbits of memory, and can process 1080p60 in 4:2:2 format on Intel Arria® 10 device. Under the same configuration the core can process 1080p30 in 4:2:2 format on Intel Max® 10 devices. Please contact CAST to discuss resource utilization and performance for your application and target device.
Contact CAST at firstname.lastname@example.org to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Bit Accurate Software Model
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Modelsim, Questa, NCSIM
Y. Altera Board Name ArriaV-GX Devkit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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