JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


This JPEG-DX-F core is an ultra-high-performance JPEG decoder supporting the Baseline and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It is suitable for decompressing JPEG images and the video payload of Motion-JPEG container formats..Depending on its configuration, the core decodes from 2 to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost effective solution for streaming or archiving UHD video, or very high frame rates at lower resolutions.Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. SoC integration is straightforward thanks to standardized AMBA' interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.


  • Standards: ISO/IEC 10918-1 Baseline (8bit) and Extended Sequential DCT (12bit) modes
  • Throughput: Synthesis-time configurable,, from 2 and up to 32 samples per clock cycle.
  • Image formats: 8bit and 12bit per color, up to 4 color-components in all widely used subsampling format, and resolution up to 64kx64k
  • Standalone operation requires no assistance from host processor.
  • Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer

Device Utilization and Performance

The JPEG-DX-F core can be mapped to any Intel® FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. The size of the core depends on its configuration. For example a core configured to process 2 pixels per cycle (JPEG-DX-F/2) occupies approximately 6,700 ALMs, 10 DSPs and 77Kbits of memory, and can process UHD/4k at 30fps on Intel Arria® 10 or Stratix® device. Under the same configuration the core can process 1080p30 in Max 10 devices. Faster processing rates are feasible in most Intel FPGAs. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at to arrange for a core evaluation

IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Software Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportDrivers are not required
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name StartixV GX and Arria V development kits
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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