The IEEE802_1AS is a complete IEEE 802.1AS hardware stack that enables the simple and rapid development of time-aware nodes for AVB/TSN networks such as automotive Ethernet. It operates fully autonomously and provides timing and synchronization according to IEEE 802.1AS for full-duplex, point-to-point Ethernet links.
The core is designed to operate next to an Ethernet Media Access Control unit (eMAC) and attached to that eMAC’s data-interface towards the host system. It automatically synchronizes its internal real-time clock (RTC) to that of the grandmaster by inserting and extracting IEEE 802.1AS frames in and from the Ethernet traffic. The core fully offloads the host processor from any IEEE 802.1AS related processing, and at the same time enables the development of time-aware applications: it provides timestamps, periodic event triggers, and alarms to the host system, using host processor Interrupt lines or dedicated-low latency interface signals.
Complete IEEE 802.1AS hardware stack enabling rapid development of time-aware AVB/TSN nodes.
Automatically synchronizes internal Real-Time Clock to Grandmaster’s time
Returns timestamps to the system using absolute time and supports programmable alarm to assert host interrupt at specified absolute time
Provides periodic event triggers, with events periods being independent from absolute time changes
Includes a QSYS project using a NIOS-based system, and an Altera Eclipse project for a sample software application
Device Utilization and Performance
The IEEE802_1AS core can be mapped to any Intel FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 4,000 ALMs. Please contact CAST to discuss resource utilization and performance for your application and target device.
Contact CAST at email@example.com to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Modelsim, Questa, NCSIM
Y. Altera Board Name Cyclone V GX Starter Kit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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