I2C-SMBUS Controller Megafunction

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The I2C-SMBUS core implements a serial interface controller for the Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The core is also suitable for the implementation of controllers for the Power Management Bus (PMbus) The core can be programmed to operate either as a bus master or slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master / slow-slave communication. Furthermore, the core detects timeout and errors to prevent from bus deadlocks and can filter-out glitches on the serial line. The control, status and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.

Features

  • Standards Compliance: Philips I2C, SMBus and PMBus
  • Operation modes: Master Transmitter, Master Receiver & Slave Transmitter

Device Utilization and Performance

I2C-SMBUS core reference designs have been evaluated in a variety of technologies. The core configured with an APB interface and the optional timer instantiated uses 281 ALMs in a Cyclone® V device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Sample SMBus software driver
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: 8-bit generic; 32-bit APB
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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