Cyclone Series:Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V
The I2C-SMBUS core implements a serial interface controller for the Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The core is also suitable for the implementation of controllers for the Power Management Bus (PMbus)
The core can be programmed to operate either as a bus master or slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master / slow-slave communication. Furthermore, the core detects timeout and errors to prevent from bus deadlocks and can filter-out glitches on the serial line.
The control, status and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.
Standards Compliance: Philips I2C, SMBus and PMBus
I2C-SMBUS core reference designs have been evaluated in a variety of technologies. The core configured with an APB interface and the optional timer instantiated uses 281 ALMs in a Cyclone® V device.
Contact CAST at email@example.com to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Sample SMBus software driver
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: 8-bit generic; 32-bit APB
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.