HSDLC: HDLC & SDLC Protocol Controller Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore

Technology: Interface Protocols: Communications

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The HSDLC core is a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80c51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The controller's great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud-rate is programmable and limited only by the link drivers and the core's clock frequency.

Features

  • Flexible Frame Formatting: Programmable preamble pattern, preamble length and inter-frame space, single- or double-byte address field,
  • Address filtering allowing multicast and broadcast, Raw transmit and receive testing modes Back-to-back transmit & back-to back receive
  • NRZ, NRZI, Bi-Phase-S, and Manchester Data Encoding, with Bit Stuffing and Bit Stripping, 16-bit (CRC-16, CCITT or IBM) and 32--bit (CRC-32) frame che
  • Flexible Serial Link Interface: Full or Half Duplex, Programmable Baud Rate, Modem Controls (RTSn/CTSn), and Collision detection
  • Internal baud generator, or external transmit clock with strobe - Automatic receive clock recovery, or external receive clock with strobe

Device Utilization and Performance

The core synthesizes to about 350 ALMs

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: APB
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated Y. Altera Board Name Cyclone IV
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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