H264-D-BP: Low-Latency AVC/H.264 Baseline Profile Decoder Core
Block Diagram
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Overview
The H264-D-BP IP core is a video decoder complying to the Constrained Baseline Profile of the AVC/H.264 standard. It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution.The decoder adds just one macroblock line of latency, which means a negligible real-world latency under one msec for most widely used video formats, including HD/720p and Full-HD/1080p video.The H264-D-BP is designed for trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds with no assistance or input from the host processor. The decoder's memory interface is extremely flexible: it operates on a separate clock domain, is independent from the external memory type, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bit stream errors to the system, and simplifies video cropping at its output.
Features
- ISO/IEC 14496-10/ITU-T H.264, Constraint Baseline Profile Decoder, up to level 4.1
- Video Formats: Progressive, 4:2:0 YCbCr with 8 bits per color sample and up to 2048x2048 pixels
- Low Latency: No decoded frame buffering - Less than 1 msec for almost all widely used video formats
- Ease of Integration: Zero CPU overhead, stand-alone operation – AXI Interfaces
- Silicon proven & Verified with Fraunhofer H.264 Compliance Test Streams suite
Device Utilization and Performance
The H264-D-BP core can be mapped to any Intel® FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. It occupies approximately 32,000 ALMs, 19 DSPs and 532Kbits of memory, and can process 1080p30 in most Intel FPGA devices.. Please contact CAST to discuss resource utilization and performance for your application and target device.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | AXI |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim, Questa, NC-SIM |
| Hardware validated | Y. Altera Board Name DK-DEV-4SGX230N & DK-START-5AGXB3N |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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