Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Stratix® IV, Stratix® V
The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
The H16550S can be run in either 16450- compatible character mode or in 16550- compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead.
The H16550S core can be utilized for many communication applications including: Serial or modem computer interface, or serial interface within modems and other devices
Independently controlled transmit, receive, line status and data set interrupts
In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
Capable of running all existing 16450 and 16550a software
Programmable baud generator
Device Utilization and Performance
The core synthesizes to about 500 LEs.
Contact CAST at email@example.com to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: APB, Generic uP
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
Y. Altera Board Name Cyclone IV, Cylcone V, Stratix IV
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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