H16550S: Synchronous 16550 UART with FIFO Core
Block Diagram
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Overview
The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16550S can be run in either 16450- compatible character mode or in 16550- compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. The H16550S core can be utilized for many communication applications including: Serial or modem computer interface, or serial interface within modems and other devices
Features
- Independently controlled transmit, receive, line status and data set interrupts
- In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
- Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Capable of running all existing 16450 and 16550a software
- Programmable baud generator
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2008 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | Other: APB, Generic uP |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim, Questa, NC-SIM |
| Hardware validated | Y. Altera Board Name Cyclone IV, Cylcone V, Stratix IV |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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