Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the industry de-facto standard Short PWM Code (SPC) protocol, and can be used for conveying data from one or multiple sensors to a centralized controller using a single SENT line.
The CSENT core can be configured as a Transmitter and/or as a Receiver, and therefore it is suitable for adding a SENT interface to devices transmitting sensor data or to controllers receiving sensor data. It provides access to its control, status, and data registers via a 32-bit APB bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The core allows for Transmitter operation without requiring any external programming or control. The reset values for all its control registers are defined at synthesis time, and at run time the system only needs to write sensor data to the core.
SENT/SAE J2716 Receiver & Transmitter, supports fast and slow channel transmit or receive, and all types of SENT frames
Supports Short PWM Code (SPC) protocol. Allows up to four sensors (transmitters) to use the same physical SENT connection
Highly programmable via 32-bit APB slave interface. Reports status on registers and on maskable interrupts.
Synthesis-time defined reset values for all registers, enables data transmit without control from host processor
Device Utilization and Performance
The CSENT core can be mapped to any Intel FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 700 ALMs, under its full configuration, and about 280 ALMs when configured as transmitter-only. Please contact CAST to discuss resource utilization and performance for your application and target device.
Contact CAST at email@example.com to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: 32-bit APB
IP-XACT Metadata included
Modelsim, Questa, NCSIM
Y. Altera Board Name DE0 nano
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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