AES-XTS: Advanced Encryption Standard Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer

Evaluation Method: OpenCore Plus

Technology: DSP

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® V


The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The XTS-X is more compact and can process 128 bits/cycle independent of the key size. The XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path.


  • AES-XTS Encryption and Decryption, compliant to to IEEE P1619™/D16 standard
  • High throughput: 128 bits/cycle (AES-XTS-X version) or 256 bits/cycle (AES-XTS-X2 version). From 20 to 40Gbps on Arria10 devices.
  • User-programmable key size of 128 or 256 bits and initialization vector of arbitrary length
  • Complete deliverables include test benches, C model and test vector generator

Device Utilization and Performance

The AES-XTS can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The core has two versions: a)\tThe AEX-XTS-X can process 128 bits/sample, occupies 4,900 ALMs and 1.8M RAM bits, and provides throughput of ~20Gbps on an Arria10 device. b)\tThe AEX-XTS-X2 can process 256 bits/sample, occupies 8,500 ALMs and 3.5M RAM bits, and provides throughput of ~40Gbps on an Arria10 device. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.

Getting Started

Contact CAST at to arrange for a core evaluation

IP Quality Metrics

Year IP was first released2010
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Software Bit Accurate Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportN/A
User InterfaceAXI; Other: Proprietary.
IP-XACT Metadata includedN
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name Aria10-GX Devkit
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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