Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Stratix® IV, Stratix® V
The AES-P encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.Two architectural versions are available to suit system requirements. The Standard version (AES32-P) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128-P) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cypher modes: ECB, CBC, OFB, CFB and CTR.The core works with a pre-expanded key, or with optional key expansion logic.
Standards: Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
Configuration: Supports ECB, CBC, OFB, CFB and CTR modes. Works with a pre-expended key or can integrate the optional key expansion function.
Throughput: standard/fast version: 2.9/11.6 Mbits/MHz for 128-bit key, 2.5/9.8 Mbits/MHz for 192-bit key, 2.1/8.5 Mbits/MHz for 256-bit key
Size: From 756 ALMs to 2,679 ALMs depending on version
Deliverables: include test benches, C model and test vector generator
Device Utilization and Performance
The core can be mapped to any Intel® FPGA Family and optimized to suit the particular project's requirements. The AES core synthesizes to 756 ALMs for the standard version and to 2,679 ALMs for the fast version. On Intel Arria® 10 device, the core can run at least 80MHz providing a throughput of 232Mbps for the standard version, or 930 Mbps for the fast version.
Contact CAST at firstname.lastname@example.org to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Bit Accurate Model
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: generic uP
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
N. Altera Board Name Altera Cyclone V SOC Board
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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