AES: Advanced Encryption Standard Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.Two architectural versions are available to suit system requirements. The Standard version (AES32) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (ECB, CBC, OFB, CFB, CTR, CCM, GCM and LRW). The core works with a pre-expanded key, or with optional key expansion logic.


  • Standards: Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
  • Throughput: standard/fast version: 2.9/11.6 Mbits/MHz for 128-bit key, 2.5/9.8 Mbits/MHz for 192-bit key, 2.1/8.5 Mbits/MHz for 256-bit key
  • Size: From 588 ALMs to 2,124 ALMs depending on version
  • Configuration: Works with a pre-expended key or can integrate the optional key expansion function
  • Deliverables: include test benches, C model and test vector generator

Device Utilization and Performance

The core can be mapped to any Intel® FPGA Family and optimized to suit the particular project's requirements. The AES core synthesizes to 588 ALMs for the standard version and to 2,124 ALMs for the fast version. On Arria10 device, the core can run at least 100MHz providing a throughput of 290Mbps for the standard version, or 1.16Gbps for the fast version.

Getting Started

Contact CAST at to arrange for a core evaluation

IP Quality Metrics

Year IP was first released2002
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Bit Accurate Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportNot required
User InterfaceOther: generic uP
IP-XACT Metadata includedN
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated N. Altera Board Name Altera Cyclone V SOC Board
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.