A429-RxTx: Multichannel ARINC 429 Receiver/Transmitter

Block Diagram

Solution Type: IP Core

End Market: Military

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The A429-RxTx IP core is a multichannel transmitter (Tx) and receiver (Rx) compliant to the ARINC 429 standard. Developed according to DO-254 ED-80 guidelines and field-proven in many civilian and military avionics systems, the core is highly reliable and ready for aviation applications. The core is designed to enable independent control of multiple Rx and Tx channels with minimum overhead for the host processor. The number of Rx and Tx channels is configurable at synthesis time. Frames are stored in 32-bit wide FIFOs of synthesis-time configurable depth. The core provides access to the FIFOs and to its status and control registers via a generic 32-bit wide interface. The data-rate and parity mode for each channel can be independently set, and receiving channels can be programmed to filter data based on the label and/or the SDI fields of the incoming frames. The core reports status and errors via its status registers, but also via a rich set of maskable interrupts.

Features

  • DO-254 Compliant, Multichannel ARINC 429 Receiver/Transmitter
  • Supports any number of Rx and Tx channels (default is 16 each)
  • Programmable data rate (12.5 or 100 kbps) and parity generation/checking (odd or even) per channel
  • Flexible received frame filtering based on Label (up to 256 different labels) and/or Source/Destination Identifier (SDI) fields
  • Reliable and Proven. Developed according to DO-254 ED-80 (DAL-A) guidelines Deployed in many military and civilian avionic systems.

Device Utilization and Performance

The A429-RxTx core can be mapped to any Intel FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 2,000 ALMs for each Rx and Tx pair. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2008
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Generic 32-bit
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name Cyclone IV
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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