Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Stratix® IV, Stratix® V
The 1553-BC/RT/MT IP core implements a serial link controller enabling the development of Bus Controllers (BC), Remote Terminals (RT), and Monitor Terminals (MT) compliant with the Department of Defense MIL-STD-1553B standard.
Field-proven in many civilian and military avionics systems and optionally accompanied by a DO-254 certification package, the core is highly reliable and ready for aviation applications.
The core can operate as a Bus Controller, Remote Terminal, and Monitor Terminal at the same time. The BC and RT modules can also be disabled at run time, or at synthesis time to reduce silicon requirements.
The 1553-BC/RT/MT is designed to enable flexible message scheduling, monitoring, and filtering for all types of traffic in different bus architectures and with minimum overhead for the host processor. Messages are conveyed to/from the host via shared memory space organized in 16-bit words, and configure the core via its 16-bit wide register interface.
DO-254 certifiable, highly-featured MIL-STD-1553B link controller. BC/RT/MT; BC-only, RT-only and Multi-RT configurations.
Supports flexible message scheduling and monitoring, and minimizes host processor load
Reliable and Proven: Deployed in many military and civilian avionic systems. Optionally delivered with DO-254 Certification Data Package
Compatible with industry-standard devices, enables use of existing software drivers and applications Special versions for legacy ICs replacement
Device Utilization and Performance
The 1553-BC/RT/MT core can be mapped to any Intel FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The core occupies approximately 6500 ALMs under its BC-only configuration, and 3000 ALMs under its RT-only configuration. Please contact CAST to discuss resource utilization and performance for your application and target device.
Contact CAST at email@example.com to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: Generic MCU I/F
IP-XACT Metadata included
Modelsim, Questa, NCSIM
Y. Altera Board Name Cyclone V (designed by customer)
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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