520N-MX
Board Image
Block Diagram
Overview
Designed for compute acceleration, the 520N-MX is a PCIe board featuring Intel’s Stratix 10 MX2100 FPGA with integrated HBM2 memory. The size and speed of HBM2 (16GB at up to 512GB/s) enables acceleration of memory-bound applications. The board’s 100G QSFP28s are ideal for clustering, and OCuLink connectors allow expansion. Both traditional HDL and higher abstraction C, C++ and OpenCL-based tool flows are supported. Deliverables include an optimized board support package (BSP) for the Intel OpenCL SDK. The 520N-MX features a Board Management Controller (BMC) for advanced system monitoring and control, which greatly simplifies platform integration and management.
Development Kit Software Contents
- (Optional) OpenCL HPC Board Support Package (BSP)
- Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application)
- Intel High-Level Synthesis (C/C++) & Quartus Prime Pro (HDL, Verilog, VHDL, etc.)
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-264-2906490311463-ds-520n-mx.pdf | Datasheet | 1 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 18.0 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | N |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
| Parts per Million (PPM) | N/A |
| Board Policy | |
| Return Material Authorization (RMA) Policy | Contact BittWare |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | Y. This applies to systems and not boards. |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application) |
|
| Additional Compliance | |
| ISO 9000 & 9001; FCC (Federal Communications Commission) |
|
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