510T
Board Image
Block Diagram
Overview
Introducing ground-breaking single precision floating point performance of up to 1.5 TFLOPS per device. The BittWare 510T Datacenter Co-Processor is a standard-height, dual-slot PCIe board designed to deliver fast and efficient performance per watt. The OpenCL-programmable 510T features two Intel Arria 10 FPGAs, along with four banks of DDR4 external memory per FPGA.
Development Kit Software Contents
- OpenCL BSP (optional)
- Quartus Prime Pro (HDL, Verilog, VHDL, etc.)
- Built-In Self-Test for CentOS 7 provided with source code
Support Document
| File Name | Description | Version |
|---|---|---|
| doc-us-dsnbk-264-5106370810946-ds-510t.pdf | Datasheet | 1 |
Board Quality Metrics
| Basic |
|
|---|---|
| Latest version of Quartus supported | 17.1 |
| Required Collateral Available | |
| User Guide | Y |
| Board Schematics | N |
| Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
| Parts per Million (PPM) | N/A |
| Board Policy | |
| Return Material Authorization (RMA) Policy | Contact BittWare |
| Compliance | |
| RoHS Compliant | Y |
| CE Compliant | N. This applies to systems and not boards. |
| Conflict Mineral Policy Compliant |
Y |
| Test Plan Summary | |
|
Built-In Self-Test for CentOS 7 provided with source code (pinout, gateware, PCIe driver & host test application) |
|
| Additional Compliance | |
| ISO 9000 & 9001 |
|
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