HDCP IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: HDMI

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Bitec HDCP IP Core is for use with the Bitec DP and HDMI IP cores. It is designed to ease the integration of content protection to FPGA and ASIC based designs with support for versions HDCP 1.3, 1.4 and 2.2.

Features

  • Supports Version 1.3, 1.4 and 2.2
  • 1-, 2- and 4-symbol/clock operation
  • Optional Key Management Service
  • Fully self contained
  • Autonomous operation

Device Utilization and Performance

TBD

Getting Started

TBD

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNOT APPLICABLE
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedCadence, Synopsis and Mentor
Hardware validated Y. Altera Board Name Arria 5
Industry standard compliance testing performed
Y
If yes, which test(s)?CTS
If yes, on which Altera device(s)?ARRIA 5
If Yes, date performed
07/01/2015
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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