DisplayPort 1.3 IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: DisplayPort

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Bitec DisplayPort Receiver intellectual property (IP) core for Intel® GX devices offers a cost-efficient alternative to ASICs and enables DTV manufacturers to rapidly develop and deliver displays offering a superior viewing experience within ever-shrinking product lifecycles.

Features

  • Supports DisplayPort 1.3 and eDP
  • MST support
  • Supports 1.62, 2.7, 5.4 and 8.1 Gbps link rates
  • 80B/10B decoder
  • Optional HDCP 1.3 and 2.2

Device Utilization and Performance

TBD

Getting Started

Hardware evaluations using Intel FPGAdev kits and Bitec Daughter card.

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportNot applicable
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedCadence, Synopsis and Mentor
Hardware validated Y. Altera Board Name Arria 10, Arria 5 and Stratix 5
Industry standard compliance testing performed
Y
If yes, which test(s)?DP CTS
If yes, on which Altera device(s)?Arria, Stratix
If Yes, date performed
12/01/2015
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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