b<>com SDR-HDR Converter

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Consumer, Medical

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10

Overview

This SDR-to-HDR technology provides a simple yet powerful way to convert SDR (Standard Dynamic Range) content into an HDR (High Dynamic Range) format. The algorithm intelligently exploits high dynamic range of the target display while carefully preserving the artistic intent of the source SDR video. • Mix of SDR and HDR live sources : Broadcasting of live events (typically sport) in HDR, using a number of cameras which are not necessarily HDR-capable, is not feasible without an SDR-to-HDR conversion. • Live Playout of SDR interstitials in a HDR program : In order to broadcast a live HDR program, the SDR-to-HDR conversion is an essential process that can be implemented either at the output of a playout server or at the input of the HDR mixer. • Conversion of legacy content to HDR For pre-recorded live and on demand service modes, extensive libraries of legacy SDR content can be preconverted to HDR (using an SDR-to-HDR file-to-file converter). • Up-conversion of legacy channels to HDR

Features

  • Converts any SDR content (without the need for input metadata), from legacy format, into a PQ/HLG or S-Log3 HDR version
  • Style-aware conversion, true to the original artistic intent
  • Lightweight process
  • Easier way to adopt HDR at production and distribution stages
  • Can be embedded in existing products

Device Utilization and Performance

FPGA target : Stratix V Arria 10, Stratix 10 Quartus report after fitting (1 instance) for Arria 10GX : ALMs needed : 1048 ALMs used in final placement : 1390 Combinational ALUTs : 1252 Dedicated Logic Registers : 2366 Block Memory Bits : 324352 M20Ks : 31 DSP Blocks : 17

Getting Started

Input video formats • All versions: HD (1920x1080p) up to 60fps (BT.709) • All versions: UHD (3840x2160p) up to 60 fps (BT.709) Output video formats Same as input video format with the following differences : • EOTF: 10 bit PQ (peak brightness of 1000 nits) or HLG or SLOG3 • Color space: BT.2020 Input video interface • FPGA version: RGB 4:4:4 10 bits on 3 internal I/O busses Output video interfaces • FPGA version: RGB 4:4:4 10 bits on 3 internal I/O busses Performance • Excellent subjective quality • FPGA version: real time conversion for UHD format FPGA IP core • SDR2HDR Software in the form of a Netlist, which can be integrated on the targeted FPGA • Lightweight process, Ultra-low latency

IP Quality Metrics

Basic
Year IP was first released2017
Latest version of Quartus supported17.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportnone
Implementation
User InterfaceAXI; Other: Avalon-stream
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim and Questa
Hardware validated Y. Altera Board Name A10_GX_HDMI
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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