b<>com HDR-SDR converter
Block Diagram
Overview
The HDR2SDR technology developed by b<>com is a smart way to produce a backward compatible SDR signal from HDR content produced in BT.2100-PQ, BT.2100-HLG or Slog3. The solution is particularly useful in situations where the same content has to be delivered simultaneously in HDR and SDR format. To preserve artistic intent, b<>com has developed an algorithm which dynamically and continuously adapts to the style of the incoming video. In addition, it is worth noting that the conversion is perfectly reversible, thanks to the award-winning SDR2HDR solution, also available from b<>com. When cascading the two conversion operations (SDR to HDR or HDR to SDR), the resulting video is visually identical to the original source. This method is sometimes referred to as a round trip. Applications : Simulcast of SDR and HDR program Conversion of HDR content to legacy format Monitoring and quality control in production environment
Features
- Converts any HDR content (without the need for input metadata) from BT.2100-PQ, BT.2100-HLG or Slog3, into a BT.1886/BT.709 SDR version.
- Lightweight process.
- Style-aware conversion and exact inverse of b<>com SDR2HDR tone expansion.
- Can be embedded in existing products
- Simpler workflow combining conversion back and forth; ensuring that artistic intent is preserved
Device Utilization and Performance
Getting Started
Input video formats : All versions: HD (1920x1080p) up to 60fps (EOTF: BT.2100-PQ or BT.2100-HLG or Slog3, Color space: BT.2020) All versions: UHD (3840x2160p) up to 60 fps (EOTF: BT.2100-PQ or BT.2100-HLG or Slog3, Color space: BT.2020) Output video formats : Same as input video format with the following differences : EOTF: BT.1886 (Gamma 2.4)• Color space: BT.709 Performance : Excellent subjective quality FPGA version: real time conversion for UHD format Input & output video interfaces : FPGA version: RGB 4:4:4 10 bits on 3 internal I/O busses FPGA IP core HDR2SDR Software in the form of a Netlist, which can be integrated on the targeted FPGA.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2017 |
| Latest version of Quartus supported | 17.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | none |
| Implementation | |
| User Interface | AXI; Other: Avalon-stream |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim and Questa |
| Hardware validated | Y. Altera Board Name A10_GX_HDMI |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | NULL |
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