SHA2-A300 Secure Hash Algorithm IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


Athena delivers Secure Hash Algorithms (SHA) as semiconductor intellectual property (IP) cores. Whether your application demands high-performance cryptographic hashing or the power savings of a dedicated core, Athena's SHA cores deliver. Athena SHA cores are compliant with FIPS 180-4.


  • DPA Countermeasures
  • Context switching
  • Available on any Intel® FPGA device

Device Utilization and Performance

Over 2.3 Gbps @ ~1000 ALUTs

Getting Started

Dedicated SHA family cores feature 32-bit and/or 64-bit data input ports and a full-width message digest output for maximum throughput and minimum latency. Input/output flow control simplifies system integration, and standard bus interfaces are available for applications that require bus connectivity. Context save and reload, automatic message padding, and HMAC features address a range of use cases. The members of the SHA family are summarized in Table 1. SHA support is also available in the EXP-F5200B cryptography microprocessor.

IP Quality Metrics

Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
By Request
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedY
Driver OS supportLinux, OpenSSL
User InterfaceAXI; Other: AHB
IP-XACT Metadata includedN
Simulators supportedall
Hardware validated Y. Altera Board Name Cyclone V, Stratix V
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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