4 STM1 CES/CEP CodeChip
Block Diagram
Overview
Arrive's Pseudowire CodeChip product line offers a family of complete pseudowire and mobile backhaul CodeChip devices. Arrive provides total solutions in groupings of 1 to 16 DS1/E1/J1 or 1 to 32 DS1/E1/J1 lines; aggregation nodes with up to 84/63 DS1/E1 lines; high-density nodes with 336/252 DS1/E1 lines; or very dense nodes with 1344/1008 DS1/E1/J1 lines. The aggregation and higher density nodes use SONET/SDH interfaces for service side connection. Arrive's CodeChips are provided in fully complete Bitstream format or encrypted netlist format along with firmware device driver/software API packages, BSP, schematic and layout reference design files, design reviews, board testing and support from initial project definition to mass production. The CodeChip Bitstreams and encrypted netlists are targeted to specific Intel® FPGA devices that are pre-selected based on the mix of features requested.
Features
- Application specific high-level API software driver
- PDH pseudowire (SAToP and CESoPSN) and SONET/SDH pseudowire (CEP) as per RFC4553, RFC5086, RFC4842
- 4xOC-3/STM-1 or 1xOC12/STM4 interfaces at service side
- 2xGbE interface: One active and one standby
- ACR/DCR clock recovery algorithm for SAToP and CESoPSN, meets ITU G.8261, G.823, G.824 and MEF22
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2008 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | OS independent |
| Implementation | |
| User Interface | Other: Local CPU buses |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Contact Arrive for more information |
| Hardware validated | Y. Altera Board Name Cyclone IV |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | Contact Arrive |
| If yes, on which Altera device(s)? | Cyclone IV |
| If Yes, date performed | 04/02/2008 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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