16-port G.Fast Switch Codechip - G.999.1 Connectivity
Block Diagram
Overview
Arrive G.Fast Switch Codechip provides two uplink ports up to 10 Gb/s and four G.999.1 ports at rate of up to 2.5 Gb/s. The FPGA-based SoC solution and external front-end devices can help to make quick-to-market distribution point equipment, specifically for Fiber-to-the-Distribution-Point (FTTdp) or to bring gigabit speeds to multiple dwelling unit (MDU) applications in access networks. Arrive's CodeChips are provided in fully complete bitstream or encrypted netlist format along with firmware device driver/software API packages, BSP, schematic and layout reference design files, design reviews, board testing and support from initial project definition to mass production. The CodeChip bitstreams and encrypted netlists are targeted to specific FPGA devices that are selected based on the mix of features requested and customer preference. CodeChips are provided with CodeChip API as a single API software driver for all CodeChip variants. CodeChip API supports protocol stack handling.
Features
- Low-cost, low-power-consumption, FPGA-based G.Fast Switch core w/single application specific high-level API software driver for all variants
- Supports protocol stack handling
- Uplinks: 2 * 1G/2.5G/10G Ethernet
- Downlinks: Up to 4 * 1G/2.5G Ethernet, each supporting up to 16 uers in G.999.1 connectivity
- Reference design with AB16-PCIeXOVR adapter board available on Altera FPGA boards
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2015 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | OS independent |
| Implementation | |
| User Interface | Other: Contact Arrive |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Contact Arrive for more information |
| Hardware validated | Y. Altera Board Name Contact Arrive for more information |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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