16-port G.Fast Switch Codechip - G.999.1 Connectivity

Block Diagram

Solution Type: IP Core

End Market: Industrial, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


Arrive G.Fast Switch Codechip provides two uplink ports up to 10 Gb/s and four G.999.1 ports at rate of up to 2.5 Gb/s. The FPGA-based SoC solution and external front-end devices can help to make quick-to-market distribution point equipment, specifically for Fiber-to-the-Distribution-Point (FTTdp) or to bring gigabit speeds to multiple dwelling unit (MDU) applications in access networks. Arrive's CodeChips are provided in fully complete bitstream or encrypted netlist format along with firmware device driver/software API packages, BSP, schematic and layout reference design files, design reviews, board testing and support from initial project definition to mass production. The CodeChip bitstreams and encrypted netlists are targeted to specific FPGA devices that are selected based on the mix of features requested and customer preference. CodeChips are provided with CodeChip API as a single API software driver for all CodeChip variants. CodeChip API supports protocol stack handling.


  • Low-cost, low-power-consumption, FPGA-based G.Fast Switch core w/single application specific high-level API software driver for all variants
  • Supports protocol stack handling
  • Uplinks: 2 * 1G/2.5G/10G Ethernet
  • Downlinks: Up to 4 * 1G/2.5G Ethernet, each supporting up to 16 uers in G.999.1 connectivity
  • Reference design with AB16-PCIeXOVR adapter board available on Altera FPGA boards

Device Utilization and Performance

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Getting Started

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IP Quality Metrics

Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportOS independent
User InterfaceOther: Contact Arrive
IP-XACT Metadata includedN
Simulators supportedContact Arrive for more information
Hardware validated Y. Altera Board Name Contact Arrive for more information
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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