Alizem DC Motor Control Embedded Software for Intel MAX10 FPGA

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus, Source Code

Technology: Processors and Peripherals: Peripherals

MAX Series: Intel® MAX® 10


Alizem DC Motor Control embedded software IP is meant to be easily, quickly and safely integrated into an Intel® MAX® 10 FPGA for use in many applications: robotics, drones, medical devices, instrumentation and consumer products. It is perfect for multi-axis applications where many multiple software instantiations can be controlled from a single NIOS® II processor with an easy to use API.


  • SCALABLE: Each block controls one motor and multiple instantiation is possible for multi-axis systems.
  • NO EXPERTISE NEEDED: No expertise in motor control or advanced FPGA design required. Keep your focus on your design.
  • EASY TO USE: DC motor control software IP block composed of a Platform Designer (formerly Qsys) component and a NIOS® II software API.
  • IoT EADY:reference design integrating Alizem IoT interface software.
  • UNIQUE: Alizem's proprietary easy-to-use API making it quick and safe to configure and operate for non-motor control nor FPGA experts.

Device Utilization and Performance

Each axis is taking under than 100LEs on Intel MAX10 FPGA. Complete reference design (including NIOS® II processor and UART) is under 2300 LEs, i.e. fits on the smallest MAX10 FPGAs.

Getting Started

1- Download datasheet for FREE on Alizem website: Choose version (demo, low-volume, IoT or open source) and download the software directly from the website.3- At the same time, you can download Alizem ebooks on custom electric motor drive design and MAX10-based embedded system design.

IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportAltera HAL
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSIm
Hardware validated Y. Altera Board Name Altera MAX10 Development Kit
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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