End Market: Automotive, Consumer, Industrial, Medical, Military, Test & Measurement
Evaluation Method: OpenCore, OpenCore Plus
Technology:Processors and Peripherals: Peripherals
Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Supported Device Family:
Alizem 3-phase PWM IP Core is meant to be easily, quickly and safely integrated into an Intel' MAX' 10 FPGA for use in many inverter-based (DC-AC) power electronics applications: pump and fan electric motor control, solar power conversion and power supplies. It is the first building block of any control system meant to drive a 3-phase 2-level inverter (6 switches) or intelligent power module (IPM).
@50 MHz clock: Tunable PWM frequency from 500 Hz to 100 kHz.
Adjustable deadtime to prevent shoot-through faults and maximize efficiency.
Voltage reference either in V(a,b,c) or V(alpha,beta) spaces.
16 bits electrical resolution.
Test mode to validate correct PWM function before connecting load.
Device Utilization and Performance
Each instantiation is taking under than 100LEs on MAX 10 FPGA. Complete reference design (including NIOS II processor) is under 2300 LEs, i.e. fits on the smallest MAX10 FPGAs.
1- Download datasheet for FREE on Alizem website: www.alizem.com/PWM 2- Choose version (demo, low-volume, IoT or source code) and download the software directly from the website. 3- At the same time, you can download Alizem ebooks on custom electric motor drive design and MAX 10-based embedded system design.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Intel MAX 10 FPGA Development kit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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