PCIe Solutions
Block Diagram
Segments:
Supported Device Family:
Solution Type:
Overview
Algo-Logic's low latency PCI express (PCIe) solutions rapidly transfer data between FPGA logic, processors, and memory. For example, in many High Frequency Trading (HFT) systems and datacenter applications, rapid data transfers are needed between FPGA logic and the Order Management System (OMS) software. For these frequent and short transactions, Algo-Logic's PCIe solutions are optimal for minimizing latency. Algo-Logic's PCIe solutions are plug-and-play; the hardware interfaces and software APIs are easy to use for software developers building low latency network streaming applications.The Register Interface supports a low latency host to FPGA communication through memory-mapped I/O (MMIO) with write combining. The Direct Memory Access (DMA) Engine is specifically designed for kernel-bypass Linux applications that require high throughput and low latency.
Device Utilization and Performance
For PCIe solutions, the device utilization on Stratix® V A7 device is:1. 15956 ALMs2. 19718 registers3. 1063424 block memory bits4. Median Latency Host to FPGA RT: 1 microseconds for 300 Byte datagram*5. P99 Latency Host to FPGA RT: 1.26 microsecond for 300 Byte datagram** Test configuration: 256 bit wide bus at 156.25Mhz clock domain on Intel i7 at 3.5Ghz.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Linux |
| Implementation | |
| User Interface | Other: Avalon ST |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim |
| Hardware validated | Y. Altera Board Name Nallatech P385, Nallatech P385A |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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