10GE MAC
Block Diagram
Overview
Algo-Logic Systems' ultra low latency (ULL) 10GE MAC minimizes roundtrip latency by several hundred nanoseconds as compared to vendor supplied IP cores. It is compatible with Intel® FPGA's PHY to make a complete solution: PHY+MAC. The design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in an FPGA by using logic optimized for latency.The ULL PHY+MAC supports SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features. The MAC interfaces to user logic via the 64-bit Avalon-ST bus or AXI4-Stream standards.The Ethernet Frame Check Sequence (FCS) within the transfer is automatically added in the transmit direction; the FCS is checked, indicated, and removed in the receive direction. The only padding done is on the transmit side (Tx) if the transmitter MAC sees fewer than 60 bytes. On the receive side (Rx), the MAC passes the packet that it receives without change.
Features
- Local fault and remote fault detection and handling.
- Reconciliation sub-layer implementation compliant with IEEE802.3.
- Latency is 89nanoseconds round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit.
- High level architecture Ethernet MAC design is flexible in its use of system clock (on the Avalon ST side).
- Automatic transmit padding, jumbo frame support, transmit and receive statistics counters.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2014 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | No CPU needed |
| Implementation | |
| User Interface | Other: Avalon ST |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim, VCS, NCSIM |
| Hardware validated | Y. Altera Board Name Terasic DE5-Net, Nallatech P385, Nallatech P385A, Bittware S5PH-Q |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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