Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Intel® Arria® 10 SoC

Stratix Series: Stratix® V


Algo-Logic Systems' ultra low latency (ULL) 10GE MAC minimizes roundtrip latency by several hundred nanoseconds as compared to vendor supplied IP cores. It is compatible with Intel® FPGA's PHY to make a complete solution: PHY+MAC. The design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in an FPGA by using logic optimized for latency.The ULL PHY+MAC supports SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features. The MAC interfaces to user logic via the 64-bit Avalon-ST bus or AXI4-Stream standards.The Ethernet Frame Check Sequence (FCS) within the transfer is automatically added in the transmit direction; the FCS is checked, indicated, and removed in the receive direction. The only padding done is on the transmit side (Tx) if the transmitter MAC sees fewer than 60 bytes. On the receive side (Rx), the MAC passes the packet that it receives without change.


  • Local fault and remote fault detection and handling.
  • Reconciliation sub-layer implementation compliant with IEEE802.3.
  • Latency is 89nanoseconds round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit.
  • High level architecture Ethernet MAC design is flexible in its use of system clock (on the Avalon ST side).
  • Automatic transmit padding, jumbo frame support, transmit and receive statistics counters.

Device Utilization and Performance

Device utilization on Stratix® V A7 is:1. Wire to wire latency: 89.6nS2. Registers: 19153. Logic utilization: 1689 ALMs4. Block memory bits: 0

Getting Started

Please visit http://algo-logic.com/phymac for more information or contact solutions@algo-logic.com

IP Quality Metrics

Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog
Software drivers providedN
Driver OS supportNo CPU needed
User InterfaceOther: Avalon ST
IP-XACT Metadata includedN
Simulators supportedModelsim, VCS, NCSIM
Hardware validated Y. Altera Board Name Terasic DE5-Net, Nallatech P385, Nallatech P385A, Bittware S5PH-Q
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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