TCP Endpoint

System Diagram

Stratix Series: Stratix® V

Altera: Intellectual Property: Accelerator Function; Segment: Data Analytics, Financial, Networking


The Algo-Logic Systems' U.S. exchange certified TCP Endpoint implements a full TCP functionality in FPGA hardware which is capable of opening, maintaining, and closing TCP Connections. It has an ultra low latency of 76-nanoseconds. The mature, reliable, and network-tested Algo-Logic Systems' TCP Endpoint delivers ultra-high performance and highest TCP bandwidth. It supports full duplex rates of 20 Gbps scalable to 140 Gbps by using multiple ports within a single FPGA. The implementation is portable to Intel® FPGA devices and compatible with all widely deployed Intel FPGA platforms including Terasic DE5Net, Solarflare AOE and other platforms. Algo-Logic’s TCP Endpoint can be seamlessly integrated with all of Algo-Logic’s existing pre-built components in the Low Latency Library.


  • Supports 32 Sessions, TCP Endpoint Termination, Proxy Mode.

Validated for use with

Quartus Prime Pro Version 17.0
Acceleration Stack version None
Xeon + FPGA Platforms supported Terasic DE5Net, Nallatech P385, Bittware S5PHQ
Device Family Stratix V
Cloud Deployments NULL

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