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JPEG Encoder Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

Our JPEG FPGA core is an 8-bit JPEG encoder for still image and video compression applications. This JPEG FPGA core is deisgned to provide extremely high speed performance, capable of compressing 140MPixels/sec for 4-2-0 and 4-2-2 images. The A2e JPEG FPGA core is also one of the smallest on the market and supports TURE grayscale mode! The core has easy to interface to FIFO interfaces on both input and output. Deliverables include a complete verification environment and bit-accurate software model.

Features

JPEG Compliance (ISO/IEC 10918-1)
High-accuracy and high-speed DCT core options
Fixed entropy table, sixteen programmable quantization tables (8 Chroma, 8 Luna)
1 clock/pixel greyscale, 1.5 clock/pixel YUV 4:2:0, 2 clock/pixel YUV 4:2:2
Custom versions available

Device Utilization and Performance

ALM: 1,100 Logic Reg: 1,351 M10K: 15 Max Freq: 110MHz

Getting Started

Please email sales@a2etechnologies.com for more details.

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	N
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	Y
Driver OS support	Linux
Implementation
User Interface	AXI
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim
Hardware validated	N. Altera Board Name NULL
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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