JPEG Encoder Core
Block Diagram

Overview
Our JPEG FPGA core is an 8-bit JPEG encoder for still image and video compression applications. This JPEG FPGA core is deisgned to provide extremely high speed performance, capable of compressing 140MPixels/sec for 4-2-0 and 4-2-2 images. The A2e JPEG FPGA core is also one of the smallest on the market and supports TURE grayscale mode! The core has easy to interface to FIFO interfaces on both input and output. Deliverables include a complete verification environment and bit-accurate software model.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
N |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | Y |
Driver OS support | Linux |
Implementation | |
User Interface | AXI |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim |
Hardware validated | N. Altera Board Name NULL |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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