JPEG Decoder Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

The A2e JPEG core performs high-speed decoding of JPEG files created by the A2e JPEG encoder, while at the same time having an extremely small FPGA resource requirement footprint. The A2e JPEG de-coder supports monochrome, YUV 4:2:0, and YUV 4:2:2 input formats.

Features

  • JPEG Compliance (ISO/IEC 10918-1)
  • Fixed entropy table, sixteen programmable quantization tables (8 Chroma, 8 Luna)
  • 1 clock/pixel greyscale, 1.5 clock/pixel YUV 4:2:0, 2 clock/pixel YUV 4:2:2
  • Single clock cycle per pixel component encoding (Monochrome)

Device Utilization and Performance

ALM: 1,100 Logic Reg: 1,351 M10K: 15 Max Freq: 110MHz

Getting Started

Please email sales@a2etechnologies.com for more details.

IP Quality Metrics

Basic
Year IP was first released2018
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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