H.264 CODEC Micro Footprint

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V


Our FPGA core is highly optimized and 80% SMALLER AND FASTER THAN THE COMPETITION WITH ⟨ 1ms LATENCY @ 1080p30! It is capable of being synthesized in many FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 95Mhz. Typical clock rate in a Xilinx Zynq 7020 is 95MHz. Multiple cores can be used for processing larger size or higher frame rate images. Uses FPGA specific DDR 3 controller and microprocessor soft core. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.


  • Fully compatible with the ITU-T H.264 specification
  • Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
  • Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution
  • Entropy Encoding: CAVLC
  • Support for intra 4 x 4 DC prediction

Device Utilization and Performance

ALM: 20,900 Logic Registers: 39,000 M10K: 116 Max Freq: 93MHz

Getting Started

To get started, please email sales@a2etechnologies.com. We can then discuss your project in detail to make sure our core will work. We can also provide a bit accurate C Model for you to evaluate the quality of the image and compression.

IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
ModelSim encrypted VHDL behavioral model
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.