Quad-SPI Serial Flash Memory Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


Quad-SPI Flash memories have many advantages : high speed, low pin count, small packages, and low cost !ALSE Quad-SPI Flash Controller IP has been designed for ultimate performance, small footprint and easy integration in all kinds of FPGAs, low-cost to high-end.Dramatically reduce the boot time, store streaming video, or even run processor code directly from the Flash, etc. The unique CFI Emulation (optional) feature further facilitates the adoption of Serial Flash memories.Supports all types of Quad SPI Flash Memories.Deliveries include a HDL simulation environment for seamless integration in any project.Our Quad-SPI controller has been used successfully by many customers in different contexts, always delivering outstanding performance.


  • Ultra High Performance. x4, Intelligent controller, Burst mode, supports the Flash maximum speed.
  • Supports almost all devices available, including very high density (devices are added regularly)
  • Supports Flash Programming (modular feature)
  • Unique CFI Flash Emulation (the serial Flash "looks like" a standard parallel NOR Flash)
  • Runs on low-cost FPGAs.

Device Utilization and Performance

Including Flash Programming :~1,100 LEs, or ~500 ALMs, 1 Memory blockFmax 175MHz on Cyclone® III and 230 MHz on Stratix® V

Getting Started

For additional information, contact ALSE : http://www.FPGA.fr !

IP Quality Metrics

Year IP was first released2012
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportCFI emulation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Most Altera FPGA kits using a Quad-SPI, AVDB, BeMicro-Max10 etc
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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