Quad-SPI Serial Flash Memory Controller
Block Diagram

Overview
Quad-SPI Flash memories have many advantages : high speed, low pin count, small packages, and low cost !ALSE Quad-SPI Flash Controller IP has been designed for ultimate performance, small footprint and easy integration in all kinds of FPGAs, low-cost to high-end.Dramatically reduce the boot time, store streaming video, or even run processor code directly from the Flash, etc. The unique CFI Emulation (optional) feature further facilitates the adoption of Serial Flash memories.Supports all types of Quad SPI Flash Memories.Deliveries include a HDL simulation environment for seamless integration in any project.Our Quad-SPI controller has been used successfully by many customers in different contexts, always delivering outstanding performance.
Features
- Ultra High Performance. x4, Intelligent controller, Burst mode, supports the Flash maximum speed.
- Supports almost all devices available, including very high density (devices are added regularly)
- Supports Flash Programming (modular feature)
- Unique CFI Flash Emulation (the serial Flash "looks like" a standard parallel NOR Flash)
- Runs on low-cost FPGAs.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | N |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | CFI emulation |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Modelsim |
Hardware validated | Y. Altera Board Name Most Altera FPGA kits using a Quad-SPI, AVDB, BeMicro-Max10 etc |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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