JPEG streaming Encoder
Block Diagram

Overview
This JPEG-Encoder IP has been designed for easy integration into all kinds of FPGAs. It has been highly optimized for a very small footprint and an excellent Fmax, enabling the use of low cost FPGAs. This IP enables FPGA-based applications to outperform DSP-based solutions and to address the most challenging markets.The JPEG-Encoder IP can compress Still Images and Video Streams and it comes with Raster-to-Block conversion integrated.Several popular input formats are supported natively (BT656, YUV, RGB), thus simplifying the connection to various image sensors or video streaming sources (Video Codecs, Ethernet streams etc).Deliverables include a very sophisticated HDL simulation environment for seamless development, verification and integrationin the final application.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | QIP File for Easy Integration |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | no driver required |
Implementation | |
User Interface | AXI; Avalon-MM; Other: Avalon ST-video |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Modelsim |
Hardware validated | Y. Altera Board Name AVDB / Clovis and many others |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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