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JPEG streaming Decoder

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

This JPEG-Decoder IP has been optimally designed for easy integration into any FPGA: the footprint is very small, thecode is portable to any vendor, and the performance (Fmax, Throughput, and Image Quality) is high.It can decode Still Images and Video Streams (Full HD, 4K). The JPEG-Decoder comes with Block to Raster Converter integrated.It is a perfect companion for the ALSE JPEG-Encoder for creating a complete compressed video transmission chain.A sophisticated HDL simulation environment is available to facilitate the integration of the IP in the customer project.

Features

Baseline JPEG-Decoder with support of any image resolution up to 64K x 64K. 4:2:0/4:2:2 Support
Standard Huffman Table / Quantization tables dynamically extracted from JPEG stream
Streaming mode (Full HD / 4K support) or Still Image
Very compact and highly optimised in Speed
Easy Integration (no need of external RAM, block-to-raster blocks provided)

Device Utilization and Performance

Decoder alone is ~3700 LEs or 1500 ALMs, 5 Memory Blocks, 9 multipliers.Fmax > 180MHz on low-cost Cyclone® IV-CV.

Getting Started

Demos are available on many existing boards, including AVDB / Clovis !Contact A.L.S.E

IP Quality Metrics

Basic
Year IP was first released	2012
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	QIP File for Easy Integration
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	no driver required
Implementation
User Interface	Other: Avalon-ST
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name AVDB / Clovis and many others
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

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