Aurora 8b10b IP Core

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Aurora 8b/10b IP Core is a lightweight protocol suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers.This IP targets Intel® FPGA devices and is compatible with the Aurora protocol. The Aurora protocol enables Intel FPGA to interconnect with other FPGAs, ASICs or ASSPs supporting the standard Aurora protocol.

Features

  • Fully compatible with the standard Aurora protocol. Full-Duplex and Simplex Tx Operations (for Simplex Rx Operation, please contact ALSE)
  • Up to 6.6 Gbps (Gigabits per seconds) per lane (depending Device Transceiver atteignable speed) and up to 16 transceiver lanes. 8b/10b encoding
  • Framing and Streaming interface, User/Native Flow Control (NFC in immediate and completion mode), CRC, Clock compensation sequence generation
  • 16 bits (2 Bytes width) and 32 bits (4 Bytes width) user datapath per XCVR lane (datapath up to 32bitsx16lanes=512bits when 16 XCVR lanes are used)
  • Available for all Intel FPGA devices with transceivers. Avalon-ST / AXI Streaming compatible

Device Utilization and Performance

Utilization :Intel® Stratix® 10 - 4 XCVR lanes - Framing - 32bits => ~3000 ALMs, 4 M20KsIntel® Arria® 10 - 1 XCVR lanes - Framing - 32bits => ~500 ALMs, 0 M10KsArria 10 - 4 XCVR lanes - Framing - 32bits => ~3500 ALMs, 4 M10KsStratix V - 1 XCVR lanes - Framing - 32bits => ~1000 ALMs, 4 M20KsStratix V - 4 XCVR lanes - Framing - 32bits => ~3100 ALMs, 8 M20KsCyclone® V - 1 XCVR lanes - Framing - 32bits => ~950 ALMs, 2 M10KsCyclone V - 4 XCVR lanes - Framing - 32bits => ~2900 ALMs, 10 M10KsNotes for above numbers : duplex mode is used, NFC/UFC are supported, CRC is disabled Performance : Link rate up to maximum device's XCVR rate (with XCVR 8b/10b feature enabled).

Getting Started

ALSE can provide : * IP in Intel FPGA IP Evaluation mode (formerly known as OpenCore Plus) for Hardware Evaluation purpose * Complete reference design on Intel Reference Kit and/or customer boards (if sufficient board info are available)

IP Quality Metrics

Basic
Year IP was first released2012
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QIP file for easy Quartus project integration
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportNone
Implementation
User InterfaceAXI; Other: Avalon-ST
IP-XACT Metadata includedN
Verification
Simulators supportedQuestaSim Modelsim
Hardware validated Y. Altera Board Name Stratix10 GX dev kit, Reflex Clovis, Reflex Attila, Reflex Achilles, ALSE HPAPB, ALSE AVDB
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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