Given the increasing demands of supporting multi-service networks in a highly flexible architecture, you need to design systems supporting an increasing list of protocols, encapsulation schemes, and data rates.

Example protocols include SONET/SDH, Ethernet, Fibre Channel, Resilient Packet Ring (RPR), Asynchronous Transfer Mode (ATM), and Frame Relay (FR). New encapsulation schemes include standards such as the emerging generic framing procedure (GFP) and virtual concatenation (VCAT), as well as High-Level Data Link Controller (HDLC) and point-to-point protocol (PPP). These technologies must also be able to scale to support rates such as 155 Mbps, 622 Mbps, 1 Gbps, 2.5 Gbps, 10 Gbps, 40 Gbps, and 100 Gbps.

You can address the mounting challenges of communication system design by integrating several functions into a high-density programmable logic device (PLD). For instance, you can integrate functions such as the SONET/SDH framer, OTU Framer, packet interface, mapping, switching, and forward error correction (FEC) into a single Altera® FPGA. Using multiple programmable files, along with the partial reconfiguration capability available in Stratix® V FPGAs, this same FPGA can be reconfigured to support multiple configurations, creating a “universal” front end.

One Altera FPGA can be designed to support the transport of LAN and WAN traffic over Optical Transport Network (OTN) networks at a variety of different data rates (155 Mbps, 622 Mbps, 2.5 Gbps, 10 Gbps, 40 Gbps, and 100 Gbps). Designing a line card to support either the transport of cells or packets over SONET/SDH as separate PLD configuration options provides a highly optimized solution. You only pay for the gates that you require and are not burdened with the complicated software programming requirements of a multi-function ASSP chipset.

Inventory costs can be further minimized while retaining flexibility by storing multiple device programming files in flash memory. The PLD can be programmed at line-card boot up with the appropriate configuration. By loading the PLD with only the required gates, the PLD size is minimized for each operating mode. The ability to partially reconfigure the device allows you to create a truly “universal” line card that is optimized for density.