Altera provides solutions to reduce media I/O costs, improve traffic aggregation, and increase packet throughput performance within routers and switches.

Overview

Ever increasing data rates, often driven by user demands for video services, continues to drive network bandwidth requirements. System designers for next-generation routers are responding with increased port speeds and refined traffic management techniques.

Figure 1. Networking Topology

The networking segment includes multiservice edge switches, edge aggregation routers, Internet protocol (IP) service routers, multiservice core switches, and IP core routers.

Typical Router Cards

The basic system architecture for an edge router is shown in Figure 1. Today’s router architectures use highly optimized network processing engines that enable the data flow of packets to proceed unimpeded along a fast path, while management functions such as route table updates are handled separately across a control plane. Line-card processing has evolved to deliver faster forwarding with deeper packet inspection. As networking requirements continue to be driven by higher wire speeds (to 100G and beyond) and more complex services driven by application-aware processing and cloud applications, new hardware is needed to accelerate these functions and keep up with customer demands.

Figure 2. Edge Aggregation Router System Diagram

Exchanging packets between media I/O cards and packet forwarding engines requires the flexibility to aggregate multiple lower rate interfaces, such as 10-Gbps Ethernet (10GbE) and 40-Gbps Ethernet (40GbE), into a higher rate interface like 100G Interlaken. A 40G to 100G packet bridge is a natural FPGA solution that can be used for traffic aggregation between framers or media access control (MAC) devices and commercial network processors.

Likewise, the need for flexible traffic management functions, optimized for each network architecture, demands the programmability and rich feature set that only an FPGA can provide.

Altera Solutions in Networking

Altera Design Advantage in Networking

  • Intel® FPGAs maximize the return on your investment across programmable networking architectures.
  • Developing routers and switches that use a programmable 10G, 40G, or 100G fast path benefits you in the following ways:
    • Reduces cost by adding features to the media I/O module without hardware replacement
    • Enables faster time to market for new features and services because deploying configuration updates is faster than redesigning and verifying new ASICs
  • Intel® Quartus® Prime design software tools provide the design and verification tools needed to speed chip development and reduce time to market.
  • Altera MegaCore® and AMPPSM intellectual property cores reduce development time by providing a wide range of industry-standard framers, data and memory interfaces, network processing unit (NPU) interfaces, and packet processing blocks to accelerate the design of networking solutions.