report_clock_network (::quartus::sta)

The following table displays information for the report_clock_network Tcl command:

Tcl Package and Version

Belongs to ::quartus::sta 1.0

Syntax report_clock_network [-h | -help] [-long_help] [-append] [-file <name> ] [-include_non_clock_paths] [-initial_depth <number> ] [-locate_with_routing] [-panel_name <name> ] [-show_full_paths] [-stdout] [-target <names> ]
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-append If output is sent to a file, this option appends the result to that file. Otherwise, the file will be overwritten. This option is not supported for HTML files.
-file <name> Sends the results to an ASCII or HTML file. Depending on the extension
-include_non_clock_paths Show paths that are potentially in the clock network. These paths terminate at a register's clock pin but do not start at a clock source.
-initial_depth <number> Initial clock network depth to report.
-locate_with_routing When locating to a path, also show detailed routing. This is only shown in Chip Planner.
-panel_name <name> Sends the results to the panel and specifies the name of the new panel
-show_full_paths Show the full clock paths - do not reduce the table size by condensing multiple trivial nodes into one row.
-stdout Send output to stdout, via messages. You only need to use this option if you have selected another output format, such as a file, and would also like to receive messages.
-target <names> Valid nodes in the clock network or clocks (string patterns are matched using Tcl string matching).
The clock network report shows the netlist topology of clock paths that make up the 
clock network in a design. It allows the user to track a clock signal from its 
source, through transformations such as PLL's, to the loads that the clock drives.
It also reveals clock relationships by indicating nodes where generated clocks are

The report can be directed to the Tcl console ("-stdout", default), a file 
("-file"), the Timing Analyzer graphical user interface ("-panel_name"), 
or any combination of the three.

Use the "-target" option to specify report targets. These can be clocks in the design or
nodes on the clock network, for example PLL outputs. If you specify clocks as targets, the 
clock network report will use the clock's target nodes as report targets. The clock network 
report then displays all nodes in the clock network that are in the fanin and fanout cones 
of the report targets. If no report target is specified, all clock target nodes in the 
design are used by default.

Each row in the report may include one node or multiple trivial nodes with singular fanin
and fanout edge. To disable the behaviour of collapsing down trivial nodes into one row, use 
the "-show_full_paths" option.

When running the clock network report in the Timing Analyzer GUI, rows in the main table 
corresponding to report target nodes are highlighted in light blue. You may click on each 
row of the table to view information such as clock frequencies, relationships, and why 
this node belongs in the clock network. You may right-click on any row to locate the
node in other Quartus tools such as RTL Viewer. You may also right-click on specific rows
to locate the shortest clock path from the clock source to that node in tools such as RTL

Use the "-initial_depth" option to reduce the height of the report table in the Timing Analyzer
GUI. Rows in the main table that are deeper than the set initial depth will be collapsed by
default, but can be manually expanded. If this option is not set, the report determines an 
appropriate initial depth to use.

Use the "-include_non_clock_paths" option if a node that you expect to be in the clock network
cannot be found. This option shows nodes that lead into a register's clock pin, but are not
downstream of any known clock source. Furthermore, registers that are not clocked by any clocks
will be shown using this option. 

Use the "-locate_with_routing" option to show the routing elements that make up a path when 
locating a path to Chip Planner. Only use this option if you use the "-target" option to specify
reporting targets, otherwise the report may be slow to generate.
Example Usage
# Report the clock network that feeds into register regA
report_clock_network -panel {Report} -target [get_registers regA]

# Report the clock network starting from clk_100 clock, but show only the first 10 levels
report_clock_network -panel {Report} -target [get_clocks clk_100] -initial_depth 10

# Report the clock network passing through the combinational node clk_mux|combout.
# In the report, include paths that end at a register's clock pin but do not start 
# at a clock source.
report_clock_network -panel {Report} -target [get_nodes clk_mux|combout] -include_non_clock_paths
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful