Synthesis Partition Reports

Synthesis generates reports to display the resource information on design partitions in the design based on the settings selected in the Design Partitions window.

Design Partition Status Report

Lists the design partition name, whether Analysis & Synthesis was performed on the partition, and the reason Synthesis ran.

Resource Utilization by Entity Report

Reports the utilization of the following resources for each partition in the design: logic cells, logic cell combinationals, logic cell registers, memory bits, block memory bits, DSP block elements, DSP block 9x9, 12x12, 18x18, and 36x36 multipliers, pins, virtual pins, the full hierarchy name, and the library name. The specific resources listed in the Compilation Report vary depending on the selected device.

Note: The logic cell combinationals count may be inaccurate if the inputs or outputs of an entity are not registered. Having unregistered inputs and outputs can cause logic to be optimized across entity boundaries, which means that logic that was originally in one entity may be named after logic in an adjacent entity and may thus be accounted towards the wrong entity.

Registers Removed During Synthesis Report

Reports information about registers removed from the design partition during Synthesis, including the register name and the reason for removal.

Partition Dependent Files Report

Lists the name of the source file that contains the entity that comprises the design partition.

Post-Synthesis Netlist Statistics for <partition_name>

Lists the netlist statistics for each partition in your design. The Type column lists the WYSIWYG primitive Definition name, including any input counts for that atom. The Count column lists the number of atoms of that type after you perform Analysis and Synthesis. Only atoms that occur in the netlist are reported.