logic cell Definition

The generic term for a basic building block of all Intel devices supported by the Quartus^® Prime software.

In supported (Arria^® series, Cyclone^® series, MAX^® II , MAX^® V, and Stratix^® series) family devices, a logic cell is the smallest unit of logic located in a LAB, and is also known as a logic element.)

In supported (Cyclone^®series, MAX^® II , and MAX^® V) family devices, a logic cell consists of a four-input LUT, a programmable register, and a carry chain. The logic cells also support a dynamic single-bit addition or subtraction mode that is selectable by a LAB-wide control signal. Each logic cell drives the local, row, column, LUT chain, register chain, and direct link interconnects. The logic cell also has ability to drive its combinational output directly to the next logic cell in the LAB using FastLUT connections.

In supported (Arria^® series and Stratix^® series) family devices, a logic cell consists of a register (lc_ff) portion, and a combinational (lc_comb) portion. Each lc_ff and lc_comb pair constitutes an Adaptive Look-Up Table (ALUT). In Stratix^® III family devices, you can implement the two combinational logic cells as register, combinational, or MLAB cells.

Two ALUTs make up an Adaptive Logic Module (ALM). Each ALUT drives the local, row, column, register chain, and direct link interconnects. The following figures show the basic architecture and numbering convention for the ALMs and ALUTs within a LAB in a

supported device (Arria^® series and Stratix^® series) family device.

Logic cells in LABs have "numbers" of the following format for the following devices: