Avalon®-ST configuration scheme (AVST) Definition

The Avalon®-ST configuration scheme uses an external host, such as a microprocessor, MAX® II , MAX® V, or MAX® 10 device. The external host controls the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host. You can use the PFL II IP core with aMAX® II, MAX® V, or MAX® 10 device as the host to read configuration data from the flash memory device and configure the Stratix® 10 device.

Options include AVST x8, AVST x16, or AVST x32. The Quartus® Prime Compiler can optionally generate compressed bitstream files.

Note: More information on the Avalon®-ST configuration scheme can be found in the Intel Stratix 10 Configuration User Guide on the Altera website.