Avalon® Memory-Mapped Interface Definition

The Avalon® Memory-Mapped interface is an interface protocol for use in connecting host and agent components in a Platform Designer system. The protocol connects address-based read/write interfaces typical of an Avalon® memory-mapped host that usually controls a number of Avalon® memory-mapped agent peripherals. The typical Avalon® memory mapped host is a microprocessor; typical agents include: memories, UARTs and timers. In contrast to the Avalon® memory mapped interface, the Avalon® Streaming interface protocol is used for very high-bandwidth, unidirectional traffic connecting source-sink pairs.

The Avalon® memory mapped interface defines:

  • A set of signal types
  • The behavior of these signals
  • The types of transfers supported by these signals

For example, you can use the memory mapped interface to describe a traditional peripheral interface, such as SRAM, that supports only simple, fixed-cycle read/write transfers. On the other hand, the memory mapped interface can also be used to describe a more complex pipelined interface capable of burst transfers.

Some of the prominent features of the Avalon® memory mapped interface are:

  • Separate Address, Data and Control Lines—provides the simplest interface to on-chip logic. By using dedicated address and data paths, Avalon® memory mapped peripherals do not need to decode data and address cycles.
  • Up to 1024-bit Data Width—supports even-power-of-two data paths, up to 1024 bits.
  • Synchronous Operation—provides an interface optimized for synchronous, on-chip peripherals. Synchronous operation simplifies the timing behavior of the Avalon® memory mapped interface, and facilitates integration with high-speed peripherals.
  • Dynamic Bus Sizing—handles the details of transferring data between peripherals with different data widths. Avalon® memory mapped peripherals with differing data widths can interface easily with no special design considerations.
  • Simplicity—provides an easy-to-understand interface protocol with a short learning curve.
  • Low resource Utilization—provides an interface architecture that conserves on-chip logic resources.
  • High performance—provides performance up to one-transfer-per-clock.