Arria® II Device Family Definition
An Intel device family based on a scalable architecture. Arria® II devices have dedicated gigabit transceiver block (GXB) circuitry that includes up to 24 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES capability at data rates up to 3.75 Gbps. They also provide dedicated circuitry that support differential I/O standards at up to 1.25 Gbps when using dynamic phase alignment (DPA). Arria® II devices also provide enhanced PLLs, fast PLLs, and regional, dual-regional, global, interquad, and periphery clock networks to increase performance, and provide advanced clock interfacing and clock-frequency synthesis.
Arria® II GX devices offer up to 16 6.375-Gbps transceivers, LVDS at 1.25 Gbps, and support for 400 MHz DD3. Arria® II GZ devices offer up to 24 6.375-Gbps transceivers, more density and memory, and higher digital signal processing (DSP) capabilities than Arria® II GX devices.
The Arria® II family device architecture supports two RAM block sizes, which are the M9K memory blocks and the MLAB. M9K and M144K memory blocks implement single-port, dual-port, and true dual-port memory. MLABs implement single-port and dual-port memory. Arria®II family devices offer support for remote configuration updates. Arria® II family devices also contain embedded DSP blocks that enable efficient implementation of high-performance filters and multipliers. The Adaptive Logic Module (ALM) of the Arria® II family device architecture provides advanced features with efficient logic utilization.
Arria® II family devices support multiple I/O transfer protocols, including PCI Express, XAUI, GIGE, SDI, Serial RapidIO, and SONET/SDH. These protocols provide high-speed communication with application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), and other programmable logic devices (PLDs). You can use both PCI Express hard IP and PCI Express soft IP to implement the physical layer, data link layer, and transaction layer of the PCI Express protocol stack. The PCI Express hard IP uses embedded dedicated logic to implement the PCI Express protocol stack.
Arria® II family devices provide up to six PLLs for each device. Arria® II devices also provide enhanced and fast PLLs. Arria® II family PLLs are capable of implementing real-time reconfiguration, clock switchover, advanced clock multiplication parameters, and fine-grain phase shifting.
Arria® II family devices support numerous single-ended and differential I/O standards.
The memory blocks of Arria® II family devices can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM; ROM; FIFO buffers; and shift registers. These blocks can also emulate SERDES functions for low-speed LVDS channels. In addition, Arria® II family device I/Os have dedicated circuitry to assist with the implementation of high-speed interfaces to external memory devices such as double data rate (DDR) SDRAM, DDR II SDRAM, DDR III SDRAM, and quad data rate (QDR) II SRAM.