ID:21372 Verilog HDL warning at <location>: VHDL unit instantiation in Verilog should have an instance name

CAUSE: Quartus Prime Synthesis generated the specified warning message for the specified location in a Design File.

ACTION: No action is required. To remove the warning, address the issue identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this warning message.