ID:15450 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK_ENABLE parameter as the other pipeline register nodes in the DSP block slice

CAUSE: The specified port of the specified WYSIWYG primitive has an illegal CLOCK_ENABLE parameter. The specified port must have the same CLOCK_ENABLE parameter as the other pipeline register nodes in the DSP block slice.

ACTION: Remove the pipeline register of the specified port of the specified WYSIWYG DSP block output, or make sure the pipeline register of the specified port uses the same CLOCK_ENABLE as the other pipeline register nodes in the DSP block slice.