ID:21202 Can't find the legal settings for PLL node "<name>" with reference clock frequency "<name>" and output clock frequency "<name>" because ES silicon LC output counter is restricted to a value of 2 (for example, values of 1, 4 and 8 are invalid)

CAUSE: The Quartus Prime software cannot find the legal settings for the specified PLL with the specified reference clock frequency and output clock frequency with ES silicon.

ACTION: Specify a legal set of reference clock frequency and output clock frequency by changing the value of base data rate to engage CGB dividers.